module rst_sync
(
    input wire  clk_i,
    input wire  rst_async_n_i,
    output reg  rst_sync_n_o
);

reg rst_s1;

always @(posedge clk or negedge rst_async_n) begin
   if(!rst_async_n) begin
       rst_s1     <= 1'b0;
       rst_sync_n <= 1'b0;
   end
   else begin
       rst_s1     <= 1'b1;
       rst_sync_n <= rst_s1;
   end
end

endmodule